1. Field of the Invention
The present invention relates to a phase locked loop, and more specifically to a circuit for detecting a lock of the phase locked loop.
2. Description of Related Art
In the prior art, one typical phase locked loop has included a phase comparator receiving an input signal and a reference signal for generating a pair of phase difference signals which assume a high logic level, respectively, when a phase coincidence is achieved. In some cases, it is necessary to detect the phase coincidence between the two input signals, namely, the phase locked condition of the phase locked loop. For this purpose, if the pair of phase difference signals are inputted to a logic gate circuit such as an AND gate (or a NAND gate), so that a high level signal (a low level signal) is generated when the phase locked loop is in a locked condition. With this arrangement, a lock condition of the phase locked loop is detected.
In the above mentioned arrangement for detecting the lock condition of the phase locked loop, however, as soon as the two input signals of the phase comparator become consistent in phase with each other, the phase lock signal is generated. This is not convenient. Namely, in the case that the phase locked loop becomes out of phase from a phase locked (or in-phase) condition and therefore operates towards an in-phase condition again, the phase of a signal to be synchronized is caused to alternately and repeatedly advance and delay with respect to the phase of a synchronizing signal, but the phase difference gradually decreases, so that, the phase of the signal to be synchronized is finally rendered consistent with the phase of the synchronizing signal. This transient characteristics will be determined by a loop gain and a damping constant of the phase locked loop, and therefore, the phase locked loop has an inherent oscillation frequency. Accordingly, in the course of the transient response of the phase locked loop, namely, in the process in which the signal to be synchronized is being brought into phase with the synchronizing signal, an erroneous lock signal is generated at each moment the two signals become instantaneously in phase.